Careers

  • 01 Physical Design

    Physical Design Engineer Responsibilities:

    • Planning integrated circuit and processor design projects and stages.
    • Collaborating on circuit engineering projects with the design team.
    • Designing layouts for processors and controller architectures.
    • Reviewing product requirements and logic diagrams.
    • Developing prototypes, testing circuit designs, and optimizing output.
    • Enabling easy routing, as well as reducing delays and resolving glitches.
    • Developing codes, as well as maintaining layout automation features and macros in layout entry tools.
    • Evaluating semiconductor devices and components, as well as performing modifications.
    • Documenting physical design processes, such as circuit layouts and device specifications.
    • Keeping informed of developments and innovation in physical design engineering.
    • Physical Design Engineer Requirements:
    • Bachelor's degree in computer engineering, electrical engineering, electronics, or related.
    • A minimum of two years' experience in physical design engineering.
    • Advanced proficiency in HDL languages, such as Verilog.
    • In-depth knowledge of design flow process control systems.
    • Experience with analog electronics and MOS transistors.
    • Great collaboration, and communication skills.
    • Superb analytical and problem-solving abilities.
    • Excellent organizational, time management, and recordkeeping skills.

    Apply

  • Python Test Automation Lead / Architect JD:

    • Job Title: Test Lead
    • Tentative start date: Mid October
    • Location: Need to be in the office when required at ADI Bangalore

    Job Responsibilities:

    • Interact with stakeholders and understand product requirements.
    • Design and develop unit and integration test cases for embedded software products.
    • Develop, maintain, and improve continuous integration frameworks and scripts
    • Help in adopting best test practices and tools in software industry
    • Ensure quality of software releases

    Skill Sets Required:

    • Electronics, Electrical or computer science graduate with 8-12 years of experience
    • Experience in writing test plans tests cases for embedded software for a minimum of 5 years
    • Hands on experience in designing and developing test software for embedded platforms for a minimum of 5 years.
    • Hands on experience in developing test codes using Python and Pytest frameworks for a minimum of 5 years
    • Hands on experience with Jenkins pipelines and groovy scripts for a minimum of 3 years.
    • Experience with Agile Software Workflows such as Scrum
    • Experience with Git, Jira and Confluence
    • Should be an expert in Python
    • Should be knowledgeable in modern trends and tools in software testing
    • Strong communication skills
    • Experience in C/C++ development desirable
    • Experience in C# test frameworks desirable
    • Experience in test automation using serial interfaces to the embedded platforms desirable.

    Apply

  • Job Description:

    • Looking for highly motivated and self-driven engineer to be part of the Verification and Applications team
    • Will be responsible for verification and validation of Versal devices for AIEngine
    • Ability to understand complex systems consisting of DSP intensive algorithms
    • Work with broader set of people/teams to rigorously test new software features working toward high quality software releases
    • Actively explores innovative methods for verification and validation of these platform designs using automated infrastructure and reduced/smaller designs
    • Uses the product as a customer would to understand strengths and areas for improvement. Performs advanced interactive testing and can assist with defining quality metrics

    Job Requirements:

    • Self-driven, motivated, focused, results oriented individual with superior academic achievements
    • Excellent communication skills for working remotely with global team
    • BS in EC/CS/EE with 7+ years or MS with 5+ years of experience in electronic design and software development
    • At least 3 year experience in verification/validation of complex designs, preferably in FPGA domain, with knowledge on latest Xilinx Tool flows
    • Domain expertise in atleast one of: Neural Networks, Data Center, Wireless applications
    • Strong understanding of Logic design, Digital Signal Processing
    • Expertise in two or more of: Python, C/C++, SystemC, HLS, System Verilog, Verilog/VHDL
    • Knowledge in debugging using simulations (Questa/VCS/etc.) as well as on boards using debugger/scopes
    • Good understanding of protocols like AXI/Etherent/PCIe etc

    Apply

  • JD for-Lead Verification Engineer:

    • Drive and lead SOC verification execution after having co-ordination with SOC (Design, DFT, PD), System and SW engineering teams.
    • Take ownership of the multiple SOC verification for the targeted functional domain.
    • Work with customer on feature requirements, use case scenarios, test plan reviews to realize the SOC is meeting all functional aspects of the targeted domain.
    • Work with architecture and design team on high level arch and use case scenarios and config space.
    • Work with IP team for IP requirement and deliverables.
    • Work with vendors and ODC members for the successful project execution
    • Work with program management team for SOC planning, schedule, resource demand/supply, critical path analysis, dev cost and execution.
    • Work with post-Si team to drive Si bring up and ramp to productization
    • Pattern Verification manager who has work experience with Patterns/Crest functional domains.
    • Develop the patterns, Verifying and delivering patterns to Product Engineering team for silicon validation.
    • Develop the test plan for the patterns at SOC level and get it reviewed with stake holders.
    • Work with IP design team for IP requirement and deliverables.
    • Work with program management team for Patterns planning, schedule, critical path analysis and execution.
    • Driving SOC verification from feature extraction to tape-out and productization.
    • Adapt the Design changes, Verification Architect, Test-plan creation, Power Reduction, Timing Convergence, test bench and test plan reviews & tape-outs.
    • Running regular execution meetings, scrums, standing meetings and resolving bottlenecks.
    • Project planning including schedule, deliverables, risk and mitigations options.
    • Drive the team for the bug free silicon deliverable

    Apply

  • Our DFT candidate should have the following skills:

    • 5-7 YearsProject in in 16nm or below, Mixed signal IC.
    • Synopsys TestMAX experience
    • Stuck-at ATPG
    • Transition fault and path-delay ATPG
    • Tester failure debug experience
    • Excellent in scripting

    Nice-to-have:

    • ATPG flow development
    • RTL DFT analysis
    • PrimeTime DFT scripting for at-speed patterns
    • SPF porting for analog-on-top design
    • BIST pattern development using Synopsys tools"

    Apply